Automatic synthesis of standard cell layouts

A method for automatically synthesizing standard cell layouts(170) given a circuit netlist, a template describing the layout style and a set of process design rules (136) starts by numerating an ordered sequence of physical netlists from the logical netlist(138). Next, a netlist is selected from the ordered sequence of physical netlists (140). Components are placed according to the selected physical netlist (144). The components are routed to implement interconnections specified by the netlist (154). The components are compacted (156). A next netlist is selected from the ordered sequence of physical netlists. The steps of placing, routing and compacting the components are repeated. The layout with the smallest width is selected(166). Finally, ies, contacts and vias are added and notches filled (170) to improve yield and performance of the circuit.