Method and apparatus for support of multiple memory types in a single memory socket architecture

An apparatus and method for supporting multiple types and configurations of random access memory devices in a single dual in line memory module (DIMM) socket architecture is provided. Typically, this architecture allows a user to select either SDRAM or EDO to be located in the socket(s) without substantially altering the connectivity between circuit components. A switching arrangement, that can be either active switches or fixed circuit traces, is used to selectively interconnect various control and addressing functions inherent in the microprocessor to appropriate pins of the memory device socket(s) depending upon whether EDO or SDRAM is used. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement that divides the address lines into two groups. The address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer/buffer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket.