Allocating registers in a superscalar machine

A register allocator is provided including a plurality of N allocatable memory cells arranged in B banks having N/B rows each so that each of the N allocatable memory cells is capable of storing a register identifier. The register allocator includes a plurality of M parallel execution write data ports coupled to the plurality of N allocatable memory cells so as to be capable of writing a de-allocated register identifier to a first associated memory cell and a plurality of M parallel execution read data ports coupled to the plurality of N allocatable memory cells so as to be capable of reading an allocated register identifier from a second associated memory cell. The register allocator includes a plurality of M (N/B)-bit write enable ports coupled to the plurality of N allocatable memory cells by N/B 1-bit write entry ports and a plurality of M (N/B)-bit read enable ports coupled to the plurality of N allocatable memory cells by N/B 1-bit read entry ports. The register allocator also includes a decoded (B- delta 1B+N/B)-bit head pointer decoded in a write decoder and coupled to the plurality of M (N/B)-bit write enable ports and a decoded (B- delta 1B+N/B)-bit tail pointer decoded in a read decoder and coupled to the plurality of M (N/B)-bit read enable ports. Up to M of the plurality of N allocatable memory cells are allocatable on a first-in-first-out basis determined by respective positions of the decoded (B- delta 1B+N/B)-bit head pointer a nd the decoded (B- delta 1B+N/B)-bit tail pointer. The respective positions of the decoded (B- delta 1B+N/B)-bit head pointer and the decoded (B- delta 1B+N/B)-bit tail pointer are separately incrementable.