Semiconductor memory device

In order to achieve a speed up of threshold value correcting operation and read operation of level detecting transistors of a semiconductor memory device and a reduction of an area of a chip thereof, a sense amplifier SA10 includes a threshold value correction driving transistor Q16 responsive to a threshold value correction drive signal RSB1 to correct levels of bit lines of data lines DL11 and DL12 with respect to threshold values of level detecting transistors Q11 and Q21 during a precharge period T2 and a read driving transistor Q15 responsive to a read control signal RS1 to activate the transistors Q11 and Q21 such that the latter transistors detect the levels of the bit lines of the data lines DL11 and DL12 during a read period T3.