Planarized plug-diode mask ROM structure

A Mask ROM and a method of manufacture of a Mask ROM on a semiconductor substrate comprises formation of a first plurality of conductor lines in a first array. A dielectric layer is formed upon the device with a matrix of openings therein in line with the first array. The openings expose the surface of the first conductor lines. Semiconductor diodes are formed in the matrix of openings in contact with the first conductor lines. A second plurality of conductor lines are formed on the surface of the dielectric layer in a second array of conductor lines orthogonal to the first plurality of conductor lines in the first array. A second plurality of conductor lines is aligned with the matrix and is in contact with the upper ends of the semiconductor diodes.