Yield improvement techniques through layout optimization

A process for optimizing the layout of an integrated circuit (IC) design is described. The optimization process includes selecting a segment of a conductive line to be modified. The segment is selected based upon its location between a first line and a second line and is separated from these lines by unequal distances, such that the segment is close enough to the first line such that a sensitive area that is susceptible to damage from particle contamination exists. The process also includes repositioning the selected segment such that the distance between the segment and the first line is increased and the distance between the segment and the second line is decreased.