Microcomputer with built-in flash memory

A microcomputer with a flash memory that solves a problem of software overload due to polling during writing or erasing of a flash memory, an interrupt caused by the completion of writing or erasing, or an interrupt caused by a monitor timer. This solution is achieved by suspending the supply of a clock signal from a clock generating circuit to a CPU, and restarting the supply of the clock signal after completion of writing or erasing. This clock signal suspension, in turn, is achieved by providing a NAND gate and an AND gate. The NAND gate NANDs a CPU rewrite mode designating signal and a write/erasure busy signal, both of which are output from a flash control circuit and are kept "1" during writing or erasing of the flash memory, thereby outputting a signal "0" during the writing or erasing. This state fixes the output of the AND gate to "0", which suspends the supply of the clock signal from the clock generator to the CPU.