System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor

An interrupt mechanism associated with a peripheral devise is connected to a processor by an interrupt driven I/O bus. The mechanism includes an n input System Interrupt Status Register (SISR) which collects up to n different interrupts from the device during a predetermined time period. Gate and timing circuits under control of signals provided by the processor regulate the frequency of the interrupts thus reducing the number of interrupt operations required to service the device.