Method and apparatus for reducing power dissipation in a precharge/discharge memory system

Method and apparatus for selectively inverting memory bits (41-49) in a memory (14). In one embodiment a master reversion bit (75) is used to indicate if all memory bits (41-49) have been inverted. In an alternate embodiment, row reversion bits (77) are used to indicate whether the bits in a corresp...

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Hauptverfasser:	MYERS, JEFFREY VAN, ELNATHAN, NATHAN
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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