Method and apparatus for reducing power dissipation in a precharge/discharge memory system

Method and apparatus for selectively inverting memory bits (41-49) in a memory (14). In one embodiment a master reversion bit (75) is used to indicate if all memory bits (41-49) have been inverted. In an alternate embodiment, row reversion bits (77) are used to indicate whether the bits in a corresponding row have been inverted. In yet another embodiment, the reversion column reversion bit (202) may be used to indicate whether the row revert bits (77) themselves have been inverted. These control bits (75, 77, 202) determine whether the output from each column of memory (14) is inverted (i.e. reverted to its original logic state) in order to provide the correct logical state at the data output of memory (14).