Control scheme for on-chip capacitor degating

A method of controlling a plurality of on-chip capacitors used to enhance power supply to logic circuits for a computer processor. The capacitors are each provided with transistors which temporarily disable the capacitors when an appropriate logic state is applied to the gate of the transistors. In this manner the effects of the capacitors upon system performance can be measured, and if a particular capacitor (or capacitor bank) is defective or presents an adverse impact, it can be permanently disabled by blowing fuses provided for each capacitor (or capacitor bank). The capacitors may be selectively disabled using a control circuit which has a multiplexer provided with a set of inputs from a register which contains a bit pattern that is used to determine which capacitors to disable. The register can be loaded with any pattern or with a pattern that corresponds to the states of the unblown fuses. Alternatively, all of the capacitors may be disabled, such as during power-on reset.