Methods of using simultaneous test verification software

Methods of speeding error analysis of electronic devices under test using simulation software that has the capability of simultaneously executing up to 32 tests on one image of the design model. One embodiment of the method contemplates executing the tests staggered in time so that a larger portion of the test is available for examination and execution at any given time. This allows errors to be found more quickly. Another embodiment contemplates more quickly testing a device initialization sequence by randomly establishing values for each state device, separately for each of the 32 tests, running the simulation, and then determining whether the state device values converge.