Circuit for logical stream sorting at CPU transfer time division for multiplexed (TDM) including bus interface circuitry

A network-to-CPU interface circuit interfaces an isochronous physical layer to an ISA bus such that a host CPU connected to the ISA bus can communicate with the isochronous physical layer. Inbound B-channel interface circuity is connectable to receive, from the isochronous physical layer, an inbound data stream which includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames. The TDM frames have a predetermined format that defines at least one logical stream such that each logical stream comprises those B-channels that are time division multiplexed into corresponding predetermined locations within the TDM frames. An inbound buffer portion of a memory is provided to hold the received inbound data stream, and an outbound buffer portion of the memory is provided for holding an outbound data stream which, like the inbound data stream, includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames. ISA bus interface circuitry is provided for channeling a selected inbound logical stream from the inbound memory buffer to the host CPU, via the ISA bus, in response to a request from the host CPU. The ISA bus interface circuitry is also for receiving a data stream from the host CPU, via the ISA bus, and for channeling that received data stream, as an outbound logical stream, to the TDM frames in the outbound memory buffer according to the predetermined format. Outbound B-channel interface circuity is provided to transmit the outbound data stream from the outbound memory buffer to the isochronous physical layer.