System and method for converting read cycles into write cycles for improved system performance

A system and method for increasing the performance of read cycles in instrumentation systems having multiple interconnected buses by converting the read cycles into write cycles and taking advantage of the write posting and FIFO buffering capabilities of the bus interface logic between each of the interconnected buses. When a requestor device desires to initiate a read cycle of memory situated on the same or a different bus, the requestor device first creates a data transfer packet containing information about the desired data. The requestor device then generates a write cycle to DMA logic situated near the memory desired to be read. The DMA logic uses the 32 bit address provided from the requestor device, to obtain information about the transfer and then initiates DMA write cycles to perform the desired transfer. Since each bus interface bridge includes write posting capability, the write operation can be performed much more efficiently than a read operation. The write posting capability requires that only (one) bus be tied up at a given time, and thus write cycles perform much more efficiently. The present invention is also capable of operating in either direction.