Computer system speed control using memory refresh counter

A computer system which provides for slowing the effective speed of a microprocessor. The microprocessor includes a disabling input that when deactivated disables operations of the microprocessor on the processor bus. A computer system according to the invention periodically deasserts this signal with the certain duty cycle, allowing the microprocessor to continue to perform necessary functions at an effective rate compatible with older microprocessors, but never requiring an actual clock frequency change. This periodic deassertion is performed in response to a memory refresh counter that periodically counts down to zero and is reloaded. By comparing an input/output register with the refresh counter, and by adjusting the input/output register, the deasserting signal to the processor is periodically deasserted with a selectable duty cycle.