Single layer polycrystalline silicon split-gate EEPROM cell having a buried control gate

An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel formed therebetween. Silicon dioxide is disposed over the drain, channel and source regions wherein the oxide overlying the drain and a portion of the channel is thicker compared to the thickness of the oxide overlying the remainder of the channel and the source. A layer of polycrystalline silicon is disposed over the channel. The buried N-plate control gate is spaced laterally from the source, drain, and channel regions. The floating gate overlying the channel extends also over the buried N-plate control gate. The split gate structure effectively realizes a pair of in-series gates, each having a different threshold voltage in accordance with the thickness of the oxide used. The voltages applied to the N-plate region are capacitively coupled to the floating gate. The potential on the floating gate in turn causes activation of the transistors formed by the split-gate structure, depending on the existing charge on the floating gate.