Adjusting prefetch size based on source of prefetch address

A prefetch unit is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. Normally, the prefetch unit performs split prefetching by generating low and high prefetch addresses in a single clock, with the high prefetch address being generated from the low prefetch address by incrementation. In cases where the low prefetch address is supplied to the prefetch unit too late in a clock period to generate the high prefetch address, such as where a branch instruction is not detected by a branch processing unit so that the target instruction address (i.e., the low prefetch address) is supplied by an address calculation stage, the prefetch unit generates a prefetch request consisting of only the low prefetch address. In an exemplary embodiment each prefetch request is for an 8 byte block of instruction bytes, such that the high prefetch address is generated by adding an 8-bit value to the low prefetch address, and, for low prefetch addresses supplied late, the prefetch unit detects whether the low prefetch address has a [0] in bit position 3, and if so, generates the high prefetch address by toggling the bit position n to a [1] (because the no carry ripple will affect the higher order bits).