Method and apparatus for fast parallel determination of queue entries

The present invention is related to a circuit useful to manage a random order queue having a plurality of queue entries, each queue entry having an associated validity bit which indicates whether the queue entry contains valid data. In one embodiment, the circuit includes a first plurality of inputs for receiving validity signals responsive to a first group of validity bits, a second plurality of inputs for receiving shift signals responsive to a second group of validity bits, and a plurality of outputs for providing select signals to multiplexers coupled to the queue, the select signals being responsive to the shift signals and the validity signals.