Method for accessing memory by activating a programmable chip select signal
A data processing system (20) having a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion alw...
Gespeichert in:
Hauptverfasser: | , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A data processing system (20) having a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match. Continued assertion reduces access time to an external device allowing the user to determine the trade-off between high speed access and low power consumption. Additionally, a speculative burst access is made without regard to match criteria, allowing a device to prepare for access while data processor (22) determines the next device to access. Here a load burst address (LBA) signal is speculatively provided to an activated device, and where the next access is to another device, the speculative access is aborted. |
---|