Method and apparatus for self-snooping a bus during a boundary transaction

Method and apparatus for self-snooping a bus during a boundary transaction

A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MERCHANT, AMIT A, RHODEHAMEL, MICHAEL W, FISCH, MATTHEW A, SARANGDHAR, NITIN V, BRAYTON, JAMES M
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.