Address calculation logic including limit checking using carry out to flag limit violation

Address calculation logic in which an adder carry out flags a segment limit violation is used, in an exemplary embodiment, in a 486 type microprocessor. An effective address adder (24) and a three input adder (26) comprise limit checking logic. The three input adder receives on offset (EA[31:0]) and two limit-checking components: the memory reference fetch size and, for the exemplary embodiment, a converted segment limit. Specifically, the segment limit from a segment descriptor is converted such that, for either expand up or expand down segments, when the offset is added to this converted segment limit and (in the case of expand up segments) the fetch size in the three input adder, a limit violation is flagged by the carry out bit of a three input adder. In the exemplary embodiment, the segment is converted at segment load and stored on-chip in a segment descriptor register.