Translating buffer and method for translating addresses utilizing invalid and don't care states

A translation buffer and method for translating a virtual address to a physical address are disclosed. The translation buffer includes a plurality of storage locations, each including a tag store for storing a virtual page number and a data store for storing an associated physical page number. Each tag store includes comparators for comparing a virtual page number specified by a virtual address to the virtual page number stored in that tag store to selected the associated physical page number when a match occurs. The comparators are responsive to "don't care" information stored in each of the storage locations, the don't care information specifying bits in the virtual page number stored in the tag store. Bits of the virtual page number and the don't care information are stored in pairs of single bit storage cells, each of the pairs encoding one of an invalid state, a logic zero state, a logic one state, and a don't care state. One of the pairs of single bit storage cells is connected to a flush line and is responsive to a flush signal for setting that one of the pairs of single bit storage cells to the invalid state. The translation buffer further includes a multiplexer which has control inputs for receiving a granularity mask stored in the storage locations. The pairs of single bit storage cells may be used in a content addressable memory adapted for use in the translation buffer for providing variable page granularity.