Semiconductor memory device with redundant circuit

A semiconductor memory device in a semiconductor memory circuit with a redundant memory, in which a redundant memory cell compulsory selection circuit is provided and a redundant memory cell compulsory selection signal and a redundant memory address are given from an external portion, whereby after performing the inspection of the redundant memory cell array in advance, the defective row or defective column of the normal memory cell array can be set to a position of the redundant memory cell array not including a defect.