Automatic delay adjustment for static timing analysis using clock edge identification and half cycle paths

An apparatus and method are disclosed that perform static timing analysis on a logic circuit. The logic circuit is unique in that it includes a path topology having a mixture of full cycle and half cycle timing paths. The apparatus and method first perform a data event identification event on the logic circuit and use this event to define a set of clock-to-data-phase transformation rules for defining in all latch instances of the circuit, how each data phase is generated and from what clock edge each data phase is created. Next, the system then performs a test edge selection and then performs a clock adjustment based on the transformation rules and the test edge selection. In performing the test edge selection, the system selects a correct time leading or time trailing edge based on which edge level of the clock is the level against which an arriving data signal to be tested. The clock adjustment is further performed by examining a test edge associated with the data phase associated with the arriving data signal to be tested, selecting a full cycle adjustment, which is the same as the edge launched by the data signal, and then performing a half cycle adjustment if the test edge is opposite the edge launched by the data signal.