Nonvolatile memory cell with P-N junction formed in polysilicon floating gate

An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages VT, and improves device life because fewer electrons travel through the gate oxide (30).