Enhanced information processing system using cache memory indication during DMA accessing

An information processing system includes a central processing unit, a main storage, a main storage controller for controlling the main storage, a cache memory having a content of at least one part of addresses stored in the main storage, at least one DMA controller which is capable of referring to the main storage and a DMA address translation unit for translating a logical address outputted from the DMA controller into a physical address for referring to the main storage. The DMA address translation unit has a flag representing whether or not the cache memory is referred to on DMA. The main storage controller performs either of reference to the cache memory or direct reference to the main storage based upon the flag on DMA.