Branch processing unit with a far target cache accessed by indirection from the target cache

A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache-the far target cache stores limits and mode bit...

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Bibliographische Detailangaben

Hauptverfasser:	MCMAHAN, STEVEN C
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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