Branch processing unit with a far target cache accessed by indirection from the target cache

A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache-the far target cache stores limits and mode bits for far targets stored in the target cache. For each far COF entry in the target cache, an FTC index field stores an index pointing to the corresponding entry in the far target cache. For far COFs that hit in the target cache, the target cache outputs corresponding far target addressing information and the associated FTC index to indirectly access the far target cache to obtain the associated segment limit information.