Microcomputer in which a CPU is operated on the basis of a clock signal input into one of two clock terminals

A microcomputer constituted so that an oscillation state selection signal indicative of whether a clock inputted to a first clock terminal is a clock generated at a clock generating circuit is given to a first gate circuit interposed between a first clock terminal and a second clock terminal, and a first gate circuit is placed in the transmissible state when an oscillation state selection signal is on a first state while a first gate circuit is placed in a state not to be able to transmit a signal when the oscillation state selection signal is on a second state.