Method and apparatus for configuration of processor operating parameters

A configuration system including a processor having memory for storing operating parameters and configuration logic for retrieving the operating parameters and configuring a computer system to achieve a desired performance level. The configuration logic preferably includes programmable regulators, such as a voltage regulator and a clock synthesizer, for asserting an operating voltage and clock signal, respectively, to the processor. These operating signals are asserted at nominal levels at start up to allow the processor to operate at a reduced, yet adequate performance level. The stored operating parameters are asserted onto a processor data bus by the processor during start up and stored in corresponding data latches. The parameters are further provided to the programmable regulators, such as a voltage regulator, a clock synthesizer, for example, which convert the operating signals from the nominal levels to optimal levels corresponding to the retrieved parameters. The operating signals may further be dynamically reconfigured by storing new parameters in the data latches, if desired. Thus, the regulators may be dynamically reconfigured during operation to achieve operating criterion, such as slowing down the clock frequency during a low power mode.