Test circuits and methods for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state

An integrated circuit including a semiconductor chip and chip circuitry including memory circuitry and additional non-memory circuitry all fabricated on the semiconductor chip. The chip circuitry has a defined set of locations having logic states including a first logic state and at least one other logic state. A semiconductor chip package has pins connected to the chip circuitry. Accumulator circuitry on-chip and connected to the chip circuitry generates a count of the number of locations in the set that have the first logic state. The semiconductor chip package has pins connected to the chip circuitry and accumulator circuitry for external access to the count. Other integrated circuits, palette devices, computer graphics systems and methods are disclosed.