Cache control for use in a multiprocessor to prevent data from ping-ponging between caches
A multiprocessor cache control uses ping-pong bits to reduces the number of invalidate cycles on a shared system bus in a multiprocessor system with a plurality of caches when data is being updated by multiple CPUs. The ping-pong bit is used predict when sharing is taking place and convert read-shar...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A multiprocessor cache control uses ping-pong bits to reduces the number of invalidate cycles on a shared system bus in a multiprocessor system with a plurality of caches when data is being updated by multiple CPUs. The ping-pong bit is used predict when sharing is taking place and convert read-shared requests into read-exclusive requests. |
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