Memory bit-line pull-up scheme

A method and apparatus for reducing noise in a memory bit-line pull-up circuit. The memory bit-line pull-up circuit includes a first reference line, a second reference line, a first capacitor, a gating device, and a pull-down circuit. The circuit may further include a load transistor coupled between the first reference line and a first voltage conduit, which generally maintains the voltage on the first reference line at Vcc-Vt, and a second capacitor and the load transistor providing a pull-up path for the voltage on the first reference line when Vcc increases and the first capacitor. The pull-down circuit provides a pull-down path for the voltage on the first reference line when Vcc decreases. The first capacitor provides a pull-up path for the voltage on the second reference line. A first gating device couples a bit-line to the first reference line. The circuit further including a second gating device to couple a bit-line bar to the first reference line. By coupling the bit-line(s) to a second reference line through the gating device(s), the gating device(s) are partially turned on during a portion of the bit-line (or bit-line bar) recovery time. In other words, when the voltage on the bit-line (or bit-line bar) is less than the voltage on the reference line, then the coupling of the noise from the bit-line onto the first reference line is generally reduced relative to coupling the bit-line(s) to ground.