Data processing system with microprocessor/cache chip set directly coupled to memory bus of narrower data width

A cache of a CPU/cache chip set, has a wide data path that is directly coupled, to a memory data bus having a narrow data path. The coupling is effected by a data transfer path comprising only conductors without any additional components that would introduce signal propagation delays. Cache data transfers are initiated by a cache controller. A bus controller provides data transfer control signals to transfer sets of data where each set has the same number of bits as the width of the memory bus. Data is transferred in burst cycles comprising a plurality of cache data transfer cycles. Each of the latter cycles comprises a plurality of memory bus cycles.