Circuitry for resetting an electrically erasable memory device

When power is turned off during erasure or writing, electric charge is left due to high voltage. This charge is discharged when the power is turned on. Thus, erroneous erasure, erroneous writing, and erroneous reading are prevented. It comprises a reset circuit 2 for producing a reset signal when the power is turned on, a bias circuit 3 for producing a given voltage during the period of the reset signal, a driver 4 for selecting and driving all word lines with a given voltage during the period of the reset signal, and discharging circuits 5 for electrically discharging all control lines and all bit lines during the period of the reset signal.