Gate array for accelerating access to a random access memory

An apparatus for rapidly determining a control parameter t=t0 at which the sum S of n functions Fi (i=1, . . . n) reaches a minimum, a maximum, or a given value, wherein each function Fi(t) changes its first derivative only at given discrete values tij of the control parameter t is described. The apparatus has a random access memory (RAM) addressed by the values tij, a circuit for summing the second derivatives of the functions, a circuit to perform a double integration to evaluate S, and a comparator to determine the optimum control value; also disclosed is a new gate array (GA) which rapidly reproduces the addresses used to address the RAM while skipping all others. This gate array is advantageously used as a part of the apparatus for determining a control parameter. Further, the use of the devices in a communication network is described.