Accelerometer-based shock/vibration testing apparatus and associated methods for a portable computer

A portable notebook computer has a shock/vibration testing system incorporated therein and including first and second memory chips and a miniature accelerometer mounted on the computer motherboard and interconnected to the power supply board and storage battery portions of the computer by a power su...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	BRIDGES, JOHN W
Format:	Patent
Sprache:	eng
Schlagworte:	ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVEREDIN A SINGLE OTHER SUBCLASS ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDEDFOR ELSEWHERE CHECKING-DEVICES GENERATING RANDOM NUMBERS INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT MEASURING MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION,OR SHOCK MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR PHYSICS REGISTERING OR INDICATING THE WORKING OF MACHINES TARIFF METERING APPARATUS TESTING TIME OR ATTENDANCE REGISTERS VOTING OR LOTTERY APPARATUS
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Beschreibung
Zusammenfassung:	A portable notebook computer has a shock/vibration testing system incorporated therein and including first and second memory chips and a miniature accelerometer mounted on the computer motherboard and interconnected to the power supply board and storage battery portions of the computer by a power supply switchover circuit. During operational periods of the computer the switchover circuit connects the power supply board output to the accelerometer input, and the accelerometer output to the first memory chip, so that accelerometer output data indicative of the operational shock/vibration loads borne by the computer is received and stored in the first memory chip. During non-operational periods of the computer the switchover circuit connects the storage battery output to the accelerometer input, and the accelerometer output to the second memory chip, so that accelerometer output data indicative of the non-operational shock/vibration loads borne by the computer is received and stored in the second memory chip. After a predetermined test period the operational and non-operational shock/vibration loading data stored in the two memory chips is retrieved and analyzed by suitable diagnostic software loaded in the computer.