Topography for integrated circuit operational amplifier

A high speed integrated circuit operational amplifier chip having first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A low gain differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. Low gain amplification circuit transistors are located adjacent to the low gain differential input circuit and disposed along the thermal centerline between the low gain differential input circuit and the output drive circuit stage to provide approximately balanced response to the low gain amplification circuit transistors to differential heating by the output driver circuit. Compensated bias current circuitry is located along the fourth edge and adjacent to the low gain amplification circuit transistors and the output driver circuit.