Method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used

A method of fabricating semiconductor devices which eliminates the need to use additional window mask process to expose topographical marks, such as alignment targets, on a wafer when chemical-mechanical polish planarization technique are used to substantially planarize the surface of the wafer prior to metal deposition. The method comprises (a) depositing a first removable layer on the wafer; (b) removing a portion of the first removable layer to form a large window around the first topographical mark and to retain an area of the first removable layer around the window; (c) forming an island of material within the: window and over the first topographical mark, wherein the island having a top surface of a second topographical mark replicating the first topographical mark; (d) depositing a second removable layer over the wafer including over the area and the island; (e) chemical-mechanical polishing the second removable layer to substantially planarize the second removable layer; and (f) removing the second removable layer deposited over the area and the island to expose the second topographical mark. The outer dimension of the window is large enough so that the upper surface of the second topographical mark and the upper surface of the material located in the remaining area on the wafer are of approximately equal spacing from the substantially planarized second removable layer. Accordingly, additional window mask process can be eliminated because one etch process, such as a contact etch, will be sufficient to expose the second topographical mark.