System for the automatic transfer of message status in digital data communication

A device for automatic transfer of status information concerning data blocks between a microprocessor controlled system and a peripheral device where a direct memory access controller (DMA) is used for transferring data. The status information concerning a certain data block is stored in status registers where the status information is received from either the microprocessor controlled system or the peripheral device. The DMA controls the transfer of data between the two systems where the blocks of data are stored in a FIFO. Each data block contains at its end an end of data indicator. A state machine and counter responds to the end of data indicator of a data block upon the completion of the transfer of the data block to generate an enabling signal for transferring the status information from the register as if it were part of the data block. This is performed in a manner transparent to the DMA and the microprocessor to obviate the need of microprocessor intervention.