Compensation circuit for input stage of high speed operational amplifier

A compensation circuit in a high speed integrated circuit operational amplifier that includes an input stage having first and second outputs connected to emitters of first and second PNP cascode transistors. A base of an cascode transistor is coupled to a collector of the first PNP cascode transistor. A resistor circuit is connected between the collectors of the second PNP cascode transistor and the NPN cascode transistor. First and second inputs of a diamond follower output buffer are connected to the collectors of the NPN cascode transistor and second PNP cascode transistor, respectively. A compensation circuit includes first and second compensation capacitors connected to the collectors of the NPN cascode transistor and the second PNP cascode transistor, respectively, to prevent instability of an output voltage of the diamond follower buffer circuit.