Reset and pulse width control circuits for high-performance multi-port memories and register files
A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. Thes...
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| creator | JOSHI RAJIV V HWANG WEI HENKELS WALTER H |
| description | A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5617047A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5617047A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5617047A3</originalsourceid><addsrcrecordid>eNqFjLsKwkAQRdNYiPoNzg8EFB-pgyjWPuqwbm6SgX0xO8HfN4i91TnF4cyL1w0ZSia0lEaXQW9udSAbg0p0ZFnsyJqpi0ID90OZIJN7EyzIj065TFGUPHwURv6eBD1nhVDHDnlZzDozrVc_Lor15fw4XUuk2CAnYxGgzfN-OG6rzb6qd_-LD5acPeQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Reset and pulse width control circuits for high-performance multi-port memories and register files</title><source>esp@cenet</source><creator>JOSHI; RAJIV V ; HWANG; WEI ; HENKELS; WALTER H</creator><creatorcontrib>JOSHI; RAJIV V ; HWANG; WEI ; HENKELS; WALTER H</creatorcontrib><description>A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970401&DB=EPODOC&CC=US&NR=5617047A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970401&DB=EPODOC&CC=US&NR=5617047A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JOSHI; RAJIV V</creatorcontrib><creatorcontrib>HWANG; WEI</creatorcontrib><creatorcontrib>HENKELS; WALTER H</creatorcontrib><title>Reset and pulse width control circuits for high-performance multi-port memories and register files</title><description>A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1997</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFjLsKwkAQRdNYiPoNzg8EFB-pgyjWPuqwbm6SgX0xO8HfN4i91TnF4cyL1w0ZSia0lEaXQW9udSAbg0p0ZFnsyJqpi0ID90OZIJN7EyzIj065TFGUPHwURv6eBD1nhVDHDnlZzDozrVc_Lor15fw4XUuk2CAnYxGgzfN-OG6rzb6qd_-LD5acPeQ</recordid><startdate>19970401</startdate><enddate>19970401</enddate><creator>JOSHI; RAJIV V</creator><creator>HWANG; WEI</creator><creator>HENKELS; WALTER H</creator><scope>EVB</scope></search><sort><creationdate>19970401</creationdate><title>Reset and pulse width control circuits for high-performance multi-port memories and register files</title><author>JOSHI; RAJIV V ; HWANG; WEI ; HENKELS; WALTER H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5617047A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1997</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>JOSHI; RAJIV V</creatorcontrib><creatorcontrib>HWANG; WEI</creatorcontrib><creatorcontrib>HENKELS; WALTER H</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JOSHI; RAJIV V</au><au>HWANG; WEI</au><au>HENKELS; WALTER H</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Reset and pulse width control circuits for high-performance multi-port memories and register files</title><date>1997-04-01</date><risdate>1997</risdate><abstract>A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
| title | Reset and pulse width control circuits for high-performance multi-port memories and register files |
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