Reset and pulse width control circuits for high-performance multi-port memories and register files

A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.