Process for controlling an overcurrent tripping device of a high-speed d.c. circuit-breaker

A process for controlling an overcurrent tripping device of a high-speed d.c. circuit breaker. The input voltage can reach a signal evaluation device for current rise rate via two different paths. The tripping of the high-speed d.c. circuit-breaker is no longer fundamentally delayed by the unavoidable delay experienced by signals applied to a filtering device. A path for the input voltage, existing in parallel to the filter path can be designed such that when the current rises very steeply, the unfiltered (and thus also undelayed) signal reaches the signal evaluation device (i.e., the signal bypasses the filter and is applied to the signal evaluation device) whereas, when the current rises more slowly, the filtered signal is evaluated.