Arbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiprocessor system

Arbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiprocessor system

The invention concerns a multiprocessor system comprising processors PU0 to PUn and a common main memory. The memory is logically divided into at least two banks M0 and M1 and is interconnected with the processors by a bus 110. By means of control lines 111 to 118 a bus protocol is established so th...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: GETZLAFF, KLAUS J, WILLE, UDO
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:The invention concerns a multiprocessor system comprising processors PU0 to PUn and a common main memory. The memory is logically divided into at least two banks M0 and M1 and is interconnected with the processors by a bus 110. By means of control lines 111 to 118 a bus protocol is established so that one of said memory banks is accessed while another one of said banks is still busy.