Base cell for BiCMOS and CMOS gate arrays
A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMO...
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| creator | SHAW CHING-HAO |
| description | A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor gates in the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites. |
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The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor gates in the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970107&DB=EPODOC&CC=US&NR=5591995A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970107&DB=EPODOC&CC=US&NR=5591995A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHAW; CHING-HAO</creatorcontrib><title>Base cell for BiCMOS and CMOS gate arrays</title><description>A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor gates in the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1997</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB0SixOVUhOzclRSMsvUnDKdPb1D1ZIzEtRADPSE0tSFRKLihIri3kYWNMSc4pTeaE0N4O8m2uIs4duakF-fGpxQWJyal5qSXxosKmppaGlpamjMWEVAKHgJkc</recordid><startdate>19970107</startdate><enddate>19970107</enddate><creator>SHAW; CHING-HAO</creator><scope>EVB</scope></search><sort><creationdate>19970107</creationdate><title>Base cell for BiCMOS and CMOS gate arrays</title><author>SHAW; CHING-HAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5591995A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1997</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHAW; CHING-HAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHAW; CHING-HAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Base cell for BiCMOS and CMOS gate arrays</title><date>1997-01-07</date><risdate>1997</risdate><abstract>A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor gates in the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PULSE TECHNIQUE SEMICONDUCTOR DEVICES |
| title | Base cell for BiCMOS and CMOS gate arrays |
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