Base cell for BiCMOS and CMOS gate arrays

Base cell for BiCMOS and CMOS gate arrays

A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMO...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SHAW, CHING-HAO
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor gates in the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.