Serial communication circuit on an LSI chip and communicating with another microcomputer on the chip

A serial communication circuit which is so configured that the sub CPU SC determines a timing of bit formats with software, specificially, that the sub CPU SC controls a level of each section or an output timing of each signal of one unit to be transmitted of data by writing specific values with software to the specific registers 3, 4, 6, 95 and so on, and also at the time of receiving, the sub CPU SC controls with software a level of each section or a timing of taking in data of each signal of one unit. Thereby, it becomes possible for the serial communication circuit to process protocols of different bit formats only by changing firmware.