Pseudo-differential sense amplifier

A pseudo-differential sense amplifier for sensing the state of an array memory cell by reference to a reference cell in a predetermined state. The sense amplifier has an input stage coupled to the array memory cell, which provides signals to a differential stage from which an output is generated. The input stage has reference and array side cascode circuits in which the components are matched on each side so as to eliminate process, temperature, and other extraneous variations from influencing the differential output. An enabling signal to the array side of the input stage is delayed with respect to the reference side such that voltage fluctuations externally introduced into the signals passed from the input stage to the differential stage do not cause erroneous switching and/or glitches to appear at the sense amplifier output. Additionally, parallel cascode and load transistors can be selectively switched into the input stage circuit to enable selectable cascode transconductance and circuit loading to effect selectable speed and/or input stage voltage swing.