Computer apparatus including a main memory prefetch cache and method of operation thereof

A computer system is provided including a main memory prefetch cache which enhances the retrieval of instructions (code and data) stored in the main memory of a computer. The computer system includes a processor and a processor cache coupled thereto. A memory controller is coupled to the processor and includes a main memory prefetch cache. The memory controller also includes control circuitry which determines if a current line requested by the processor is stored in the prefetch cache, and if so, the memory controller retrieves the current line from the prefetch cache and provides the current line to the processor. The next line is then retrieved from the main memory and is overwritten over the current line in the prefetch cache. Otherwise, if the memory controller determines that the prefetch cache does not contain the current line requested by the processor, then the current line is retrieved from the main memory and is provided to the processor. The next line is then retrieved from the main memory and is stored in the prefetch cache at a register location which was occupied by the least recently used line in the cache. The invention includes circuitry and methodology for determining the least recently used line stored within the prefetch cache.